The StatInf solution is based on a statistics-oriented patented technology which validates the design of embedded systems and ensures an important decrease of the development cycle and energy consumption, while assuring safeness in critical areas.

The solution is adapted for large programs on heterogeneous multicore processors, while validating changes within programs in few minutes, even for programs for which the designers have no access to the code of programs. By combining optimization and statistical methods, StatInf not only makes it possible to make predictable the use of multi-core in the critical ES but to reduce the development cycle, to safely introduce Artificial Inteligence into the control loop, to minimize energy consumption.

StatInf’s technology is based on two main parts: statistical methods analysing traces of execution and representative protocol measurements. These measurement protocols are defined for each family of microcontrollers in order to collect representative execution traces with respect to the operation safety.

The StatInf solution provides the main advantages to our customers: 

  • Build provable embedded systems that meet safety criteria and/or standards (such as DO-178 in avionics) at the software level;
  • Analyze third-parts programs for which IP barriers do not allow to examine the code; 
  • Optimize their software/hardware architecture for better computational and energy performance with a decrease ratio up to 60%;

Guarantee development cycle times to control their costs by automating and shortening the test phase from weeks to minutes


Extreme value theory makes it possible to build a maximum bound if a principle of convergence of execution times is observed, i.e. the software constructing this bound must determine the parameters of the laws governing this convergence.

Architecture Processor Configuration

Our statistical methods analyze program execution traces and the variation of the various input and output parameters to validate any future behaviour from a representative set of traces.

The representative set is built for each program, identifying which input parameters allow to visit different paths of the algorithm implemented by the program.

Code coverage

Assuring a robustness of the pWCET estimation (all the paths of the program have been visited at least once).

For certification purpose we target 100% code coverage.

Managing interferences

We use statistical tests to understand the temporal properties of the programs: execution time, execution frequency, the relationship between its execution time and the associated energy consumption.

This allows us to identify interferences between programs, establishing the impact programs may have on each other’s executions with the aim of minimizing their impact on the performance of the embedded system.


StatInf’s approach is based on a statistical characterization of the processors and an equivalence relationship between the programs in relation to the measurement protocols, which allows a correct estimation of the execution times.

This will give us an automatic argumentation for meeting certification standards while ensuring the identification of multi-core interferences between programs with the aim of minimizing their impact on the performance of the embedded system.